View MAX9768_4593271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX9768 mono 10w class d speaker amplifier provides high-quality, efficient audio power with an inte- grated volume control function. the MAX9768 features a 64-step dual-mode (analog or digitally programmable) volume control and mute func- tion. the audio amplifier operates from a 4.5v to 14v single supply and can deliver up to 10w into an 8 ? speaker with a 14v supply. a selectable spread-spectrum mode reduces emi-radiat- ed emissions, allowing the device to pass emc testing with ferrite bead filters and cable lengths up to 1m. the MAX9768 can be synchronized to an external clock, allowing synchronization of multiple class d amplifiers. the MAX9768 features high 77db psrr, low 0.08% thd+n, and snr up to 97db. robust short-circuit and thermal-overload protection prevent device damage during a fault condition. the MAX9768 is available in a 24-pin thin qfn-ep (4mm x 4mm x 0.8mm) package and is specified over the extended -40? to +85? tem- perature range. applications features ? 10w output (8 ? , pv dd = 14v, thd+n = 10%) ? patented spread-spectrum modulation ? meets en55022b emc with ferrite bead filters ? amplifier operation from 4.5v to 14v supply ? 64-step integrated volume control (i 2 c or analog) ? low 0.08% thd+n (r l = 8 ? , p out = 6w) ? high 77db psrr ? two t on times offered MAX9768?20ms MAX9768b?5ms ? low-power shutdown mode (0.5 a) ? short-circuit and thermal-overload protection MAX9768 10w mono class d speaker amplifier with volume control ________________________________________________________________ maxim integrated products 1 19-0854; rev 0; 9/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration located at end of data sheet. ordering information note: all devices are specified over the -40? to +85? oper- ating temperature range. + denotes lead-free package. * ep = exposed pad. part pin-package t on (ms) pkg code MAX9768etg+ 24 tqfn-ep* 220 t2444+4 MAX9768betg+ 24 tqfn-ep* 15 t2444+4 mute shdn speaker audio input filterless class d speaker output analog or i 2 c volume control 3.3v 4.5v to 14v MAX9768 simplified block diagram MAX9768 emi with ferrite bead filters (v dd = 12v, 1m cable, 8 ? load) frequency (mhz) 900 800 100 200 300 500 600 400 700 5 10 15 20 amplitude (db v/m) 25 30 35 40 0 0 1000 over 20db margin to en55022b limit notebook computers flat-panel displays multimedia monitors gps navigation systems security/personal mobile radio
MAX9768 10w mono class d speaker amplifier with volume control 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (pv dd = 12v, v dd = 3.3v, gnd = pgnd = 0v, v shdn = v dd , v mute = 0v; max volume setting; speaker load resistor connected between out+ and out-, r l = , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r f = 30k ? , ssm mode. filterless modulation mode (see the functional diagram/typical application circuit ). t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pv dd to pgnd........................................................-0.3v to +16v v dd to gnd ..............................................................-0.3v to +4v sclk, sda/vol to gnd ..........................................-0.3v to +4v fb, syncout ............................................-0.3v to (v dd + 0.3v) boot_ to out_........................................................-0.3v to +4v out_ to gnd ...........................................-0.3v to (pv dd + 0.3v) pgnd to gnd ......................................................-0.3v to +0.3v any other pin to gnd ..............................................-0.3v to +4v out_ short-circuit duration.......................................continuous continuous current (pv dd , pgnd, out_) ..........................2.2a continuous input current (any other pin) .......................?0ma continuous input current (fb_) .......................................?0ma continuous power dissipation (t a = +70?) single-layer board: 24-pin thin qfn 4mm x 4mm, (derate 20.8mw/? above +70?) .................................1.67w multilayer board: 24-pin thin qfn 4mm x 4mm, (derate 27.8mw/? above +70?) .................................2.22w ja , single-layer board...........................................?48?/w ja , multilayer board ...................................................?36?/w operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units general speaker supply voltage range pv dd inferred from psrr test 4.5 14.0 v supply voltage range v dd inferred from psrr and uvlo test 2.7 3.6 v i vdd 7 14.2 filterless modulation 4 7.6 quiescent current i pvdd classic pwm modulation 4 7.6 ma shutdown current i shdn i shdn = i pvdd + i dd , shdn = gnd 0.5 50 ? filterless modulation, v mute = v dd , t a = +25? 2 ?2.5 output offset v os filterless modulation, v mute = 0v, t a = +25? 2 ?4 mv MAX9768 220 turn-on time t on MAX9768b 15 ms common-mode bias voltage v bias 1.5 v input amplifier output- voltage swing high v oh specified as v dd - v oh r l = 2k ? connect to 1.5v 3.6 100 mv input amplifier output- voltage swing low v ol specified as v ol - gnd r l = 2k ? connect to 1.5v 6 50 mv input amplifier output short-circuit current limit ?0 ma input amplifier gain- bandwidth product gbw 1.8 mhz speaker amplifiers internal gain a vmax max volume setting; from fb to amplifier outputs |(out+) - (out-)|; excludes external gain resistors 29.27 30.1 31.00 db
MAX9768 10w mono class d speaker amplifier with volume control _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units filterless modulation 87 efficiency (note 2) p out = 8w, f in = 1khz, r l = 8 ? classic pwm modulation 85 % r l = 8 ? , thd+n = 1%, filterless modulation 1.3 pv dd = 5v r l = 8 ? , thd+n = 10%, filterless modulation 1.7 r l = 8 ? , thd+n = 10%, classic pwm modulation 9 pv dd = 12v r l = 8 ? , thd+n = 10%, filterless modulation 9 r l = 8 ? , thd+n = 10%, classic pwm modulation 10 output power (note 2) p out pv dd = 14v r l = 8 ? , thd+n = 10%, filterless modulation 10 w soft output current limit i lim 1.75 2 a hard output current limit i sc 2.5 a filterless modulation 0.09 total harmonic distortion plus noise (note 2) thd+n f = 1khz, r l = 8 ? , p out = 5w classic pwm modulation 0.08 % ffm 94 unweighted ssm 93 ffm 97 0db = 8w, r l = 8 ? , bw = 22hz to 22khz, filterless modulation mode a-weighted ssm 97 ffm 93 unweighted ssm 89 ffm 97 signal-to-noise ratio (note 2) snr 0db = 8w, r l = 8 ? , bw = 22hz to 22khz, classic pwm modulation a-weighted ssm 91 db mute attenuation (note 3) 0db = 8w, f = 1khz 115 db v dd = 2.7v to 3.6v, filterless modulation , t a = +25? 52 68 pv dd = 4.5v to 14v, filterless modulation , t a = +25? 67 84 f = 1khz, v ripple = 200mv p-p on pv dd 77 power-supply rejection ratio psrr f = 1khz, v ripple = 100mv p-p on v dd 60 db sync = gnd 1060 1200 1320 sync = unconnected 1296 1440 1584 oscillator frequency f ocs sync = v dd (spread-spectrum modulation mode) 1200 ?0 khz electrical characteristics (continued) (pv dd = 12v, v dd = 3.3v, gnd = pgnd = 0v, v shdn = v dd , v mute = 0v; max volume setting; speaker load resistor connected between out+ and out-, r l = , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r f = 30k ? , ssm mode. filterless modulation mode (see the functional diagram/typical application circuit ). t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX9768 10w mono class d speaker amplifier with volume control 4 _______________________________________________________________________________________ electrical characteristics (continued) (pv dd = 12v, v dd = 3.3v, gnd = pgnd = 0v, v shdn = v dd , v mute = 0v; max volume setting; speaker load resistor connected between out+ and out-, r l = , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r f = 30k ? , ssm mode. filterless modulation mode (see the functional diagram/typical application circuit ). t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units sync = gnd 265 300 330 sync = unconnected 324 360 396 class d switching frequency sync = v dd (spread-spectrum modulation mode) 300 ?.5 khz sync frequency lock range 1000 1600 khz minimum sync frequency lock duty cycle 40 % maximum sync frequency lock duty cycle 60 % gain matching full volume (ideal matching for r in and r f )2% into shutdown 52.6 out of shutdown 48 into mute 67 click-and-pop level (note 2) k cp peak voltage, 32 samples per second, a-weighted, r in x c in 10ms to guarantee clickless/popless operation out of mute 57 dbv input impedance dc volume control mode (sda/vol) 100 m ? input hysteresis dc volume control mode (sda/vol) 11 mv 9.5db gain voltage dc volume control mode (sda/vol) 0.1 x v dd v full mute voltage dc volume control mode (sda/vol) 0.9 x v dd v digital inputs ( shdn , mute, addr1, addr2, sync) sync 2.33 input-voltage high v ih all other pins 0.7 x v dd v sync 0.8 input-voltage low v il all other pins 0.3 x v dd v i sync ?.5 ?3 input leakage current i lk all other digital inputs ? ? digital output (syncout) output-voltage high load = 1ma v dd - 0.3 v output-voltage low load = 1ma 0.3 v rise/fall time c l = 10pf 5 ns
MAX9768 10w mono class d speaker amplifier with volume control _______________________________________________________________________________________ 5 electrical characteristics (continued) (pv dd = 12v, v dd = 3.3v, gnd = pgnd = 0v, v shdn = v dd , v mute = 0v; max volume setting; speaker load resistor connected between out+ and out-, r l = , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r f = 30k ? , ssm mode. filterless modulation mode (see the functional diagram/typical application circuit ). t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units thermal protection thermal shutdown threshold 150 ? thermal shutdown hysteresis 15 ? digital inputs (sclk, sda/vol) input-voltage high v ih 0.7 x v dd v input-voltage low v il 0.3 x v dd v input high leakage current i ih v in = v dd ? ? input low leakage current i il v in = gnd ? ? input hysteresis 0.1 x v dd v input capacitance c in 5pf digital outputs (sda/vol) output high current i oh v oh = v dd 1a output low voltage v ol i ol = 3ma 0.4 v i 2 c timing characteristics (figure 3) serial clock f scl 400 khz bus free time between a stop and start condition t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat 0 0.9 ? data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.6 ? rise time of sda and scl, receiving t r (note 4) 20 + 0.1cb 300 ns fall time of sda and scl, receiving t f (note 4) 20 + 0.1cb 300 ns
MAX9768 10w mono class d speaker amplifier with volume control 6 _______________________________________________________________________________________ note 1: all devices are 100% production tested at t a = +25?. all temperature limits are guaranteed by design. note 2: testing performed with a resistive load in series with an inductor to simulate an actual speaker load. for r l = 8 ? , l = 68?. note 3: device muted by either asserting mute or minimum v ol setting. note 4: c b = total capacitance of one bus line in pf. electrical characteristics (continued) (pv dd = 12v, v dd = 3.3v, gnd = pgnd = 0v, v shdn = v dd , v mute = 0v; max volume setting; speaker load resistor connected between out+ and out-, r l = , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r f = 30k ? , ssm mode. filterless modulation mode (see the functional diagram/typical application circuit ). t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units fall time of sda, transmitting t f (note 4) 20 + 0.1cb 250 ns pulse width of spike suppressed t sp 050ns capacitive load for each bus line c b 400 pf total harmonic distortion plus noise vs. frequency MAX9768 toc01 frequency (hz) thd+n (%) 10k 1k 100 0.1 1 10 0.01 10 100k pv dd = 12v r l = 8 ? filterless modulation output power = 6w output power = 2w total harmonic distortion plus noise vs. frequency MAX9768 toc02 frequency (hz) thd+n (%) 10k 1k 100 0.1 1 10 0.01 10 100k pv dd = 12v r l = 8 ? pwm mode output power = 5w output power = 2w total harmonic distortion plus noise vs. frequency MAX9768 toc03 frequency (hz) thd+n (%) 10k 1k 100 0.1 0.01 1 10 0.001 10 100k pv dd = 5v r l = 8 ? filterless modulation output power = 1w output power = 300mw typical operating characteristics (pv dd = 12v, v dd = 3.3v = gnd = pgnd = 0v, v mute = 0v; 0db volume setting; all speaker load resistors connected between out+ and out-, r l = 8 ? , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r fb = 30k ? , spread-spectrum modulation mode.)
MAX9768 10w mono class d speaker amplifier with volume control _______________________________________________________________________________________ 7 total harmonic distortion plus noise vs. frequency MAX9768 toc04 frequency (hz) thd+n (%) 10k 1k 100 0.1 0.01 1 10 0.001 10 100k pv dd = 5v r l = 8 ? pwm mode output power = 300mw output power = 800mw total harmonic distortion plus noise vs. frequency MAX9768 toc05 frequency (hz) thd+n (%) 0.1 0.01 1 10 0.001 pv dd = 12v r l = 8 ? filterless modulation p out = 4w 10k 1k 100 10 100k fixed-frequency modulation spread-spectrum modulation MAX9768 toc06 frequency (hz) thd+n (%) 0.1 0.01 1 10 0.001 pv dd = 12v r l = 8 ? pwm mode p out = 4w total harmonic distortion plus noise vs. frequency 10k 1k 100 10 100k fixed-frequency modulation spread-spectrum modulation total harmonic distortion plus noise vs. output power MAX9768 toc07 output power (w) thd+n (%) 10 8 46 2 0.1 0.01 1 100 10 0.001 012 pv dd = 12v r l = 8 ? filterless modulation f in = 10khz f in = 100hz f in = 1khz total harmonic distortion plus noise vs. output power MAX9768 toc08 output power (w) thd+n (%) 10 8 46 2 0.1 0.01 1 100 10 0.001 0 pv dd = 12v r l = 8 ? pwm mode f in = 10khz f in = 100hz f in = 1khz total harmonic distortion plus noise vs. output power MAX9768 toc09 output power (w) thd+n (%) 2.0 1.0 1.5 0.5 0.1 0.01 1 100 10 0.001 0 pv dd = 5v r l = 8 ? filterless modulation f in = 10khz f in = 100hz f in = 1khz total harmonic distortion plus noise vs. output power MAX9768 toc10 output power (w) thd+n (%) 2.0 0.8 1.2 1.6 0.4 0.1 0.01 1 100 10 0.001 0 pv dd = 5v r l = 8 ? pwm mode f in = 10khz f in = 100hz f in = 1khz total harmonic distortion plus noise vs. output power MAX9768 toc11 output power (w) thd+n (%) 10 468 2 0.1 1 100 10 0.01 0 pv dd = 12v r l = 8 ? f in = 1khz filterless modulation fixed-frequency modulation spread-spectrum modulation total harmonic distortion plus noise vs. output power MAX9768 toc12 output power (w) thd+n (%) 10 468 2 0.1 1 100 10 0.01 0 pv dd = 12v r l = 8 ? f in = 1khz pwm mode fixed-frequency modulation spread-spectrum modulation typical operating characteristics (continued) (pv dd = 12v, v dd = 3.3v = gnd = pgnd = 0v, v mute = 0v; 0db volume setting; all speaker load resistors connected between out+ and out-, r l = 8 ? , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r fb = 30k ? , spread-spectrum modulation mode.)
MAX9768 10w mono class d speaker amplifier with volume control 8 _______________________________________________________________________________________ efficiency vs. output power MAX9768 toc13 output power (w) efficiency (%) 10 468 2 20 10 30 50 40 60 100 80 70 90 0 0 pwm mode pv dd = 12v f in = 1khz r l = 8 ? filterless modulation efficiency vs. output power MAX9768 toc14 output power (w) efficiency (%) 2.0 1.0 1.5 0.5 20 10 30 50 40 60 100 80 70 90 0 0 pwm mode filterless modulation pv dd = 5v f in = 1khz r l = 8 ? efficiency vs. supply voltage MAX9768 toc15 supply voltage (v) efficiency (%) 14.5 8.5 10.5 12.5 6.5 83 86 89 95 92 80 4.5 thd+n = 10% thd+n = 1% f in = 1khz r l = 8 ? filterless modulation efficiency vs. supply voltage MAX9768 toc16 supply voltage (v) efficiency (%) 14.5 8.5 10.5 12.5 6.5 83 86 89 95 92 80 4.5 f in = 1khz r l = 8 ? pwm modulation thd+n = 10% thd+n = 1% output power vs. supply voltage MAX9768 toc17 supply voltage (v) output power (w) 14 81012 6 2 4 6 8 14 12 10 0 4 r l = 8 ? f in = 1khz pwm mode thd+n = 10% thd+n = 1% output power vs. supply voltage MAX9768 toc18 supply voltage (v) output power (w) 14 81012 6 2 4 6 8 12 10 0 4 r l = 4 ? f in = 1khz pwm mode thd+n = 1% thd+n = 10% output power vs. load resistance MAX9768 toc19 load resistance ( ? ) output power (w) 30 10 15 25 20 5 2 4 6 8 12 10 0 0 pv dd = 12v f = 1khz pwm mode thd+n = 1% thd+n = 10% output power vs. load resistance MAX9768 toc20 load resistance ( ? ) output power (w) 30 10 15 25 20 5 0.5 1.0 1.5 2.5 2.0 3.5 3.0 0 0 pv dd = 5v f = 1khz pwm mode thd+n = 1% thd+n = 10% typical operating characteristics (continued) (pv dd = 12v, v dd = 3.3v = gnd = pgnd = 0v, v mute = 0v; 0db volume setting; all speaker load resistors connected between out+ and out-, r l = 8 ? , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r fb = 30k ? , spread-spectrum modulation mode.) case temperature vs. output power MAX9768 toc21 output power (w) case temperature ( c) 12 46 10 8 2 10 30 20 40 50 70 60 90 80 0 0 f in = 1khz r l = 8 ? pv dd = 14v pv dd = 12v
MAX9768 10w mono class d speaker amplifier with volume control _______________________________________________________________________________________ 9 power-supply rejection ratio (pv dd ) vs. frequency MAX9768 toc22 frequency (hz) psrr (db) 100k 1k 10k 100 -90 -70 -80 -60 -50 -30 -40 0 -10 -20 -100 10 pv dd = 12v v ripple = 100mv p-p r l = 8 ? pwm mode filterless modulation power-supply rejection ratio (v dd ) vs. frequency MAX9768 toc23 frequency (hz) psrr (db) 100k 1k 10k 100 -90 -70 -80 -60 -50 -30 -40 0 -10 -20 -100 10 v dd = 3.3v v ripple = 100mv p-p r l = 8 ? pwm mode filterless modulation output waveform (filterless modulation) MAX9768 toc24 1 s/div 5v/div 5v/div output waveform (pwm mode) MAX9768 toc25 1 s/div 5v/div 5v/div output frequency spectrum MAX9768 toc26 frequency (khz) 20 10 515 -120 -100 -80 -40 -60 0 -20 -140 0 ffm mode v in = -60dbv f = 1khz r l = 8 ? unweighted output magnitude (dbv) output frequency spectrum MAX9768 toc27 frequency (khz) 20 10 515 -120 -100 -80 -40 -60 0 -20 -140 0 v in = -60dbv f = 1khz r l = 8 ? unweighted output magnitude (dbv) wideband output spectrum (fixed-frequency modulation mode) MAX9768 toc28 frequency (mhz) 1000 10 100 -90 -100 -80 -70 -30 -40 -50 -60 0 -10 -20 1 rbw = 10khz input ac grounded filterless modulation output amplitude (dbv) wideband output spectrum (fixed-frequency modulation mode) MAX9768 toc29 frequency (mhz) 1000 10 100 -90 -100 -80 -70 -30 -40 -50 -60 0 -10 -20 1 rbw = 10khz input ac grounded pwm mode output amplitude (dbv) wideband output spectrum (spread-spectrum modulation mode) MAX9768 toc30 frequency (mhz) 1000 10 100 -90 -100 -80 -70 -30 -40 -50 -60 0 -10 -20 1 output amplitude (dbv) rbw = 10khz input ac grounded filterless modulation _______________________________________________________________________________________ 9 typical operating characteristics (continued) (pv dd = 12v, v dd = 3.3v = gnd = pgnd = 0v, v mute = 0v; 0db volume setting; all speaker load resistors connected between out+ and out-, r l = 8 ? , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r fb = 30k ? , spread-spectrum modulation mode.)
MAX9768 10w mono class d speaker amplifier with volume control 10 ______________________________________________________________________________________ wideband output spectrum (spread-spectrum modulation mode) MAX9768 toc31 frequency (mhz) 1000 10 100 -90 -100 -80 -70 -30 -40 -50 -60 0 -10 -20 1 output amplitude (dbv) rbw = 10khz input ac grounded pwm mode turn-on/off response (MAX9768) MAX9768 toc32 100ms/div shdn 2v/div out 500ma/div turn-on/off response (MAX9768b) MAX9768 toc33 40ms/div shdn 2v/div out 500ma/div volume control level vs. volume control voltage MAX9768 toc34 v vol (v) 3.5 2.0 1.5 1.0 0.5 3.0 2.5 -100 -80 -60 -20 -40 20 0 -120 0 volume level (db) supply current (pv dd ) vs. supply voltage MAX9768 toc35 supply voltage (v) 14 10 8 612 0.5 1.0 1.5 3.0 2.0 2.5 4.0 3.5 0 4 supply current (ma) pwm mode r l = filterless modulation supply current (v dd ) vs. supply voltage MAX9768 toc36 supply voltage (v) 3.6 3.2 3.0 2.8 3.4 7 9 13 11 15 5 2.6 supply current (ma) pwm mode filterless modulation shutdown current vs. supply voltage MAX9768 toc37 supply voltage (v) 14 10 8 612 0.35 0.45 0.40 0.50 0.30 4 shutdown current ( a) shutdown current = i pvdd + i dd v dd = 3.3v typical operating characteristics (continued) (pv dd = 12v, v dd = 3.3v = gnd = pgnd = 0v, v mute = 0v; 0db volume setting; all speaker load resistors connected between out+ and out-, r l = 8 ? , unless otherwise noted. c bias = 2.2?, c1 = c2 = 0.1?, c in = 0.47?, r in = 20k ? , r fb = 30k ? , spread-spectrum modulation mode.)
MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 11 pin description pin name function 1, 2 out+ positive speaker output 3, 16 pv dd speaker amplifier power-supply input. bypass with a 1? capacitor to ground. 4 boot+ positive speaker output boost flying-capacitor connection. connect a 0.1? ceramic capacitor between boot+ and out+. 5 sclk i 2 c serial-clock input and modulation scheme select. in i 2 c mode (addr1 and addr2 gnd) acts as i 2 c serial-clock input. when addr1 and addr2 = gnd. connect sclk to v dd for classic pwm modulation, or connect sclk to ground for filterless modulation. 6 sda/vol i 2 c serial data i/o and analog volume control input 7fb feedback. connect feedback resistor between fb and in to set amplifier gain. see the adjustable gain section. 8 in audio input 9, 11 gnd ground 10 bias common-mode bias voltage. bypass with a 2.2? capacitor to gnd. 12 sync frequency select and external clock input. sync = gnd: fixed-frequency mode with f s = 1200khz. sync = unconnected: fixed-frequency mode with f s = 1440khz. sync = v dd : spread-spectrum mode with f s = 1200khz ?0khz. sync = clocked: fixed-frequency mode with f s = external clock frequency. 13 syncout clock signal output 14 v dd power-supply input. bypass with a 1? capacitor to gnd. 15 boot- negative speaker output boost flying-capacitor connection. connect a 0.1? ceramic capacitor between bootl- and outl-. 17, 18 out- negative speaker output 19 shdn shutdown input. drive shdn low to disable the audio amplifiers. connect shdn to v dd for normal operation 20 mute mute input. drive mute high to mute the speaker outputs. connect mute to gnd for normal operation. 21, 22 pgnd power ground 23 addr2 address select input 2. i 2 c address option, also selects volume control mode. 24 addr1 address select input 1. i 2 c address option, also selects volume control mode. ep ep exposed pad. connect the exposed thermal pad to gnd, and use multiple vias to a solid copper area on the bottom of the pcb.
detailed description the MAX9768 10w, class d audio power amplifier with spread-spectrum modulation provides a significant step forward in switch-mode amplifier technology. the MAX9768 offers class ab performance with class d efficiency and a minimal board space solution. this device features a wide supply voltage operation (4.5v to 14v), analog or digitally adjusted volume control, exter- nally set input gain, shutdown mode, sync input and output, speaker mute, and industry-leading click-and- pop suppression. the MAX9768 features a 64-step, dual-mode (analog or i 2 c programmed) volume control and mute function. in analog volume control mode, voltage applied to sda/vol sets the volume level. two address inputs (addr1, addr2) set the volume control function between analog and i 2 c and set the slave address. in i 2 c mode there are three selectable slave addresses allowing for multiple devices on a single bus. spread-spectrum modulation and synchronizable switching frequency significantly reduce emi emis- sions. the outputs use maxim? low-emi modulation scheme with minimum pulse outputs when the audio inputs are at the zero crossing. as the input voltage increases or decreases, the duration of the pulse at one output increases while the other output pulse dura- tion remains the same. this causes the net voltage across the speaker (v out+ - v out- ) to change. the minimum-width pulse topology reduces emi and increases efficiency. MAX9768 10w mono class d speaker amplifier with volume control 12 ______________________________________________________________________________________ mute volume control class d shutdown control oscillator syncout bias 14 v dd v dd pv dd c bias 2.2 f 7 8 1, 2 4 17, 18 15 10 13 fb r f 30k ? r in 20k ? c in 0.47 f c1 0.1 f c2 0.1 f 1 f 1 f in 20 19 6 5 24 23 gnd pgnd out+ boot+ out- boot- bias 12 3, 16 9, 11 21, 22 2.7v to 3.6v 4.5v to 14v sync mute shdn sda/vol sclk addr1 addr2 i 2 c analog control MAX9768 (shown in analog volume contol mode, a v = 23.5db, f -3db = 17hz, spread-spectrum modulation mode, filterless modulation mode, mute off) functional diagram/typical application circuit
operating modes fixed-frequency mode the MAX9768 features two fixed-frequency modes: 300khz and 360khz. connect sync to gnd to select 300khz switching frequency; leave sync unconnected to select 360khz switching frequency. the frequency spectrum of the MAX9768 consists of the fundamental switching frequency and its associated harmonics (see the wideband output spectrum graphs in the typical operating characteristics ). for applications where exact spectrum placement of the switching fundamen- tal is important, program the switching frequency so the harmonics do not fall within a sensitive frequency band (table 1). audio reproduction is not affected by chang- ing the switching frequency. spread-spectrum mode the MAX9768 features a unique, patented spread- spectrum mode that flattens the wideband spectral components, improving emi emissions that may be radiated by the speaker and cables. this mode is enabled by setting sync = v dd (table 1). in ssm mode, the switching frequency varies randomly by ?.5khz around the center frequency (300khz). the modulation scheme remains the same, but the period of the triangle waveform changes from cycle to cycle. instead of a large amount of spectral energy present at multiples of the switching frequency, the energy is now spread over a bandwidth that increases with frequency. above a few megahertz, the wideband spectrum looks like white noise for emi purposes. a proprietary amplifi- er topology ensures this does not corrupt the noise floor in the audio bandwidth. external clock mode the sync input allows the MAX9768 to be synchro- nized to an external clock, or another maxim class d amplifier, creating a fully synchronous system, minimiz- ing clock intermodulation, and allocating spectral com- ponents of the switching harmonics to insensitive frequency bands. applying a clock signal between 1mhz and 1.6mhz to sync synchronizes the MAX9768. the class d switching frequency is equal to one-fourth the sync input frequency. syncout is equal to the sync input frequency and allows several maxim amplifiers to be cascaded. the synchronized output minimizes interference due to clock intermodulation caused by the switching spread between single devices. the modulation scheme remains the same when using syncout, and audio reproduction is not affected (figure 1). current flowing between syncout of a master device and sync of a slave device is low as the sync input is high imped- ance (typically 200k ? ). MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 13 table 1. operating modes sync oscillator frequency (khz) class d frequency (khz) gnd fixed-frequency modulation with f osc = 1200 fixed-frequency modulation with f osc = 300 unconnected fixed-frequency modulation with f osc = 1440 fixed-frequency modulation with f osc = 360 v dd spread-spectrum modulation with f osc = 1200 ?0 spread-spectrum modulation with f osc = 300 ?.5 clocked fixed-frequency modulation with f osc = external clock frequency fixed-frequency modulation with f osc = external clock frequency / 4 syncout out+ out- out+ out- sync MAX9768 MAX9768 figure 1. cascading two amplifiers
filterless modulation/pwm modulation the MAX9768 features two output modulation schemes: filterless modulation or classic pwm, selec- table through sclk when the device is in analog mode (addr2 and addr1 = gnd, table 2) or through the i 2 c interface (table 7). maxim? unique, filterless modu- lation scheme eliminates the lc filter required by tradi- tional class d amplifiers, reducing component count, conserving board space and system cost. although the MAX9768 meets fcc and other emi limits with a low- cost ferrite bead filter, many applications still may want to use a full lc-filtered output. if using a full lc filter, the performance is best with the MAX9768 configured for classic pwm output. switching between schemes while in normal operating mode with the i 2 c interface, the output is not click-and- pop protected. to have click-and-pop protection when switching between output schemes, the device must enter shutdown mode and be configured to the new out- put scheme before the startup sequence is terminated. the startup time for the MAX9768 is typically 220ms. the startup time for the MAX9768b is typically 15ms. efficiency efficiency of a class d amplifier is due to the switching operation of the output stage transistors. in a class d amplifier, the output transistors act as current-steering switches and consume negligible additional power. any power loss associated with the class d output stage is mostly due to the i 2 r loss of the mosfet on- resistance, and quiescent-current overhead. the theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the MAX9768 still exhibits > 80% efficiencies under the same conditions (figure 2). soft current limit when the output current exceeds the soft current limit, 2a (typ), the MAX9768 enters a cycle-by-cycle current- limit mode. in soft current-limit mode, the output is clipped at 2a. when the output decreases so the out- put current falls below 2a, normal operation resumes. the effect of soft current limiting is a slight increase in distortion. most applications will not enter soft current- limit mode unless the speaker or filter creates imped- ance nulls below 8 ? . MAX9768 10w mono class d speaker amplifier with volume control 14 ______________________________________________________________________________________ table 2. modulation scheme selection in analog mode addr2 addr1 sda/vol sclk function 0 0 analog volume control 0 filterless modulation 0 0 analog volume control 1 classic pwm (50% duty cycle) efficiency vs. output power MAX9768 fig02 output power (w) efficiency (%) 8 6 4 2 10 20 30 40 50 60 70 80 90 100 0 010 MAX9768 class ab pv dd = 12v f in = 1khz r l = 8 ? figure 2. MAX9768 efficiency vs. class ab efficiency
MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 15 hard current limit when the output current exceeds the hard current limit, 2.5a (typ), the MAX9768 disables the outputs and initi- ates a startup sequence. this startup sequence takes 220ms for the MAX9768 and 15ms for the MAX9768b. the shutdown and startup sequence is repeated until the output fault is removed. when in hard current limit, the output may make a soft clicking sound. the aver- age supply current is relatively low, as the duty cycle of the output short is brief. most applications will not enter hard current-limit mode unless the output is short cir- cuited or incorrectly connected. thermal shutdown when the die temperature exceeds the thermal shut- down threshold, +150? (typ), the MAX9768 outputs are disabled. when the die temperature decreases below +135? (typ), normal operation resumes. the effect of thermal shutdown is an output signal turning off for approximately 3s in most applications, depend- ing on the thermal time constant of the audio system. most applications should never enter thermal shut- down. some of the possible causes of thermal shut- down are too low of a load impedance, high ambient temperature, poor pcb layout and assembly, or exces- sive output overdrive. shutdown the MAX9768 features a shutdown mode that reduces power consumption and extends battery life. driving shdn low places the device in low-power (0.5?) shut- down mode. connect shdn to digital high for normal operation. in shutdown mode, the outputs are high impedance, syncout is pulled high, the bias voltage decays to zero, and the common-mode input voltage decays to zero. the i 2 c register retains its contents during shutdown. undervoltage lockout (uvlo) the MAX9768 features an undervoltage lockout protec- tion that shuts down the device if either of the supplies are too low. the device will go into shutdown if v dd is less than 2.5v (v dd uvlo = 2.5v) or if pv dd is less than 4v (pv dd uvlo = 4v). mute function the MAX9768 features a clickless/popless mute mode. when the device is muted, the outputs do not stop switching, only the volume level is muted to the speak- er. to mute the MAX9768, drive mute to logic-high. mute should be held high during system power-up and power-down to ensure optimum click-and-pop performance. volume control the volume control operates from either an analog volt- age input or through the i 2 c interface. the volume con- trol has 64 levels, with the lowest setting equal to mute. to set the device to analog mode, connect addr1 and addr2 to gnd. in analog mode, sda/vol is an ana- log input for volume control, see the functional diagram/typical application circuit . the analog input range is ratiometric between 0.9 x v dd and 0.1 x v dd , where 0.9 x v dd = full mute and 0.1 x v dd = full volume (table 6). in i 2 c mode, volume control for the speaker is controlled separately by the command register (tables 4, 5, 6). see the write data format section for more information regarding formatting data and tables to set volume levels. i 2 c interface the MAX9768 features an i 2 c 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the MAX9768 and the master at clock rates up to 400khz. when the MAX9768 is used on an i 2 c bus with multiple devices, the v dd supply must stay pow- ered on to ensure proper i 2 c bus operation. the mas- ter, typically a microcontroller, generates scl and initiates data transfer on the bus. figure 3 shows the 2- wire interface timing diagram. a master device communicates to the MAX9768 by trans- mitting the proper address followed by the data word. each transmit sequence is framed by a start (s) or repeated start (s r ) condition and a stop (p) condi- tion. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. the MAX9768 sda line operates as both an input and an open-drain output. a pullup resistor, greater than 500 ? , is required on the sda bus. the MAX9768 scl line operates as an input only. a pullup resistor, greater than 500 ? , is required on scl if there are multiple mas- ters on the bus, or if the master in a single-master sys- tem has an open-drain scl output. series resistors in line with sda and scl are optional. the scl and sda inputs suppress noise spikes to assure proper device operation even on a noisy bus.
MAX9768 10w mono class d speaker amplifier with volume control 16 ______________________________________________________________________________________ bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). sda and scl idle high when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 4). a start (s) condition from the master signals the beginning of a transmission to the MAX9768. the mas- ter terminates transmission, and frees the bus, by issu- ing a stop (p) condition. the bus remains active if a repeated start (sr) condition is generated instead of a stop condition. early stop conditions the MAX9768 recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. slave address the slave address of the MAX9768 is 8 bits and con- sisting of 3 fields: the first field is 5 bits wide and is fixed (10010). the second is a 2-bit field, which is set through addr2 and addr1 (externally connected as logic-high or low). third field is a r/ w flag bit. set r/ w = 0 to write to the slave. a representation of the slave address is shown in table 3. when addr1 and addr2 are connected to gnd, seri- al interface communication is disabled. table 4 sum- marizes the slave address of the device as a function of addr1 and addr2. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX9768 uses to handshake receipt each byte of data (figure 5). the MAX9768 pulls down sda during the master-generated 9th clock pulse. the sda line must remain stable and low during the high period of the acknowledge clock pulse. monitoring ack allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master can re- attempt communication. scl sda start condition stop condition repeated start condition start condition t hd,sta t su,sta t hd,sta t sp t buf t su,sto t low t su,dat t hd,dat t high t r t f figure 3. 2-wire serial-interface timing diagram scl sda ssrp figure 4. start, stop, and repeated start conditions
write data format a write to the MAX9768 includes transmission of a start condition, the slave address with the r/ w bit set to 0 (see table 3), one byte of data to the command register, and a stop condition. figure 6 illustrates the proper format for one frame. volume control the command register is used to control the volume level of the speaker amplifier. the two msbs (d7 and d6) should be set to 00 to choose the speaker register. v5?0 is the volume control data that will be written into the addresses register to set the volume level (see tables 5 and 6). for a write byte operation, the master sends a single byte to the slave device (MAX9768). this is done as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 data bits. 5) the active slave asserts an ack (or nack) on the data line. 6) the master generates a stop condition. MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 17 table 3. slave address block sa7 (msb) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (lsb) 1 0 0 1 0 addr2 addr1 r/ w table 4. slave address addr2 addr1 slave address 0 0 disabled 0 1 1001001_ 1 0 1001010_ 1 1 1001011_ 1 scl start condition sda 289 clock pulse for acknowledgment acknowledge not acknowledge figure 5. acknowledge s slave address 7 bits write byte format wr ack data 8 bits ack p data byte: gives a command. slave address: equivalent to chip- select line of a 3- wire interface. 0 figure 6. write data format example
MAX9768 10w mono class d speaker amplifier with volume control 18 ______________________________________________________________________________________ table 5. data byte format d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) 0 0 v5 v4 v3 v2 v1 v0 table 6. speaker volume levels v5 v4 v3 v2 v1 v0 volume position volume level (db) step size (db) 1 1 1 1 1 1 63 9.5 0.7 1 1 1 1 1 0 62 8.8 0.7 1 1 1 1 0 1 61 8.2 0.6 1 1 1 1 0 0 60 7.6 0.6 1 1 1 0 1 1 59 7.0 0.6 1 1 1 0 1 0 58 6.5 0.5 1 1 1 0 0 1 57 5.9 0.5 1 1 1 0 0 0 56 5.4 0.5 1 1 0 1 1 1 55 4.9 0.5 1 1 0 1 1 0 54 4.4 0.5 1 1 0 1 0 1 53 3.9 0.6 1 1 0 1 0 0 52 3.4 0.4 1 1 0 0 1 1 51 2.9 0.5 1 1 0 0 1 0 50 2.4 0.4 1 1 0 0 0 1 49 2.0 0.4 1 1 0 0 0 0 48 1.6 0.4 1 0 1 1 1 1 47 1.2 0.7 1 0 1 1 1 0 46 0.5 1.0 101101 45 -0.5 1.5 101100 44 -1.9 1.5 101011 43 -3.4 1.5 101010 42 -5.0 1.1 101001 41 -6.0 1.1 101000 40 -7.1 1.8 100111 39 -8.9 1.0 100110 38 -9.9 1.0 100101 37 -10.9 1.1 100100 36 -12.0 1.2 100011 35 -13.1 1.3 100010 34 -14.4 0.9 100001 33 -15.4 1.0 100000 32 -16.4 1.1
MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 19 table 6. speaker volume levels (continued) v5 v4 v3 v2 v1 v0 volume position volume level (db) step size (db) 011111 31 -17.5 2.2 011110 30 -19.7 1.9 011101 29 -21.6 1.9 011100 28 -23.5 1.7 011011 27 -25.2 2.0 011010 26 -27.2 2.6 011001 25 -29.8 1.6 011000 24 -31.5 2.0 010111 23 -33.4 2.5 010110 22 -36.0 1.6 010101 21 -37.6 2.0 010100 20 -39.6 2.5 010011 19 -42.1 1.6 010010 18 -43.7 2.0 010001 17 -45.6 2.5 010000 16 -48.1 2.5 001111 15 -50.6 3.5 001110 14 -54.2 2.5 001101 13 -56.7 3.5 001100 12 -60.2 2.5 001011 11 -62.7 3.5 001010 10 -66.2 2.5 001001 9 -68.7 3.5 001000 8 -72.2 2.5 000111 7 -74.7 3.5 000110 6 -78.3 2.5 000101 5 -80.8 3.5 000100 4 -84.3 2.5 000011 3 -86.8 3.5 000010 2 -90.3 2.5 000001 1 -92.8 0 0 0 0 0 0 0 (mute) -161.5
MAX9768 10w mono class d speaker amplifier with volume control 20 ______________________________________________________________________________________ applications information filterless class d operation the MAX9768 can be operated without a filter and meet common emc radiation limits when the speaker leads are less than approximately 10cm. lengths beyond 10cm are possible but should be verified against the appropriate emc standard. select the filter- less modulation mode with spread-spectrum modula- tion mode for best performance. for longer speaker wire lengths, a simple ferrite bead and capacitor-based filter can be used to meet emc limits. see figure 7 for the correct connections of these components. select a ferrite bead with 100 ? to 600 ? impedance, and rated for at least 1.5a. the capacitor value will vary based on the ferrite bead chosen and the actual speaker lead length. select the capacitor value based on emc performance. when doing bench evaluation without a filter or a ferrite bead filter, include a series inductor (68? for 8 ? load) to model the actual loudspeaker? behavior. if this inductance is omitted, the MAX9768 will have reduced efficiency and output power, as well as worse thd+n performance. table 7. setting class d output modulation scheme d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) function 1 1 0 1 0 1 0 1 classic pwm 1 1 0 1 0 1 1 0 filterless modulation* boot_+ c1 0.1 f c9 330pf c10 330pf out_+ boot_- c2 0.1 f out_- MAX9768 figure 7. ferrite bead filter * power-on default.
inductor-based output filters some applications will use the MAX9768 with a full inductor-/capacitor-based (lc) output filter. this is common for longer speaker lead lengths, and to gain increased margin to emc limits. select the pwm output mode and use fixed-frequency modulation mode for best audio performance. see figure 8 for the correct connections of these components. the component selection is based on the load imped- ance of the speaker. table 8 lists suggested values for a variety of load impedances. inductors l3 and l4, and capacitor c15 form the pri- mary output filter. in addition to these primary filter components, other components in the filter improve its functionality. capacitors c13 and c14, plus resistors r6 and r7, form a zobel at the output. a zobel corrects the output loading to compensate for the rising imped- ance of the loudspeaker. without a zobel, the filter will have a peak in its response near the cutoff frequency. capacitors c11 and c12 provide additional high-fre- quency bypass to reduce radiated emissions. adjustable gain gain-setting resistors external feedback resistors set the gain of the MAX9768. the output stage has an internal 20db gain in addition to the externally set gain. set the maximum gain by using resistors r f and r in (figure 9 ) as follows: choose r f between 10k ? and 50k ? . please note that the actual gain of the amplifier is dependent on the vol- ume level setting. for example, with the volume control set to +9.5db, the amplifier gain would be 9.5db + 20db, assuming r f = r in . the input amplifier can be configured into a variety of circuits. the fb terminal is an actual operational ampli- fier output, allowing the MAX9768 to be configured as a summing amplifier, a filter, or an equalizer, for example. a r r vv v f in / = ? ? ? ? ? ? ? 10 MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 21 boot_+ c1 0.1 f out_+ l4 4 1, 2 c11 c15 r6 MAX9768 c13 l3 14, 18 15 boot_- c2 0.1 f out_- c12 r7 r l c14 figure 8. output filter for pwm mode table 8. suggested values for lc filter r l ( ? ) l3, l4 (?) c15 (?) c11, c12 (?) r6, r7 ( ? ) c13, c14 (?) 6 15 0.33 0.01 7.5 0.68 8 22 0.22 0.01 10 0.47 12 33 0.1 0.01 15 0.33
MAX9768 10w mono class d speaker amplifier with volume control 22 ______________________________________________________________________________________ power supplies the MAX9768 has different supplies for each portion of the device, allowing for the optimum combination of headroom power dissipation and noise immunity. the speaker amplifiers are powered from pv dd and can range from 4.5v to 14v. the remainder of the device is powered by v dd . power supplies are independent of each other so sequencing is not necessary. power may be supplied by separate sources or derived from a sin- gle higher source using a linear regulator to reduce the voltage as shown in figure 10. component selection input filter an input capacitor, c in , in conjunction with the input resistor of the MAX9768 forms a highpass filter that removes the dc bias from an incoming signal. the ac- coupling capacitor allows the amplifier to automatically bias the signal to an optimum dc level. assuming zero source impedance, the -3db point of the highpass filter is given by: choose c in so f -3db is well below the lowest frequency of interest. use capacitors whose dielectrics have low- voltage coefficients, such as tantalum or aluminum elec- trolytic. capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low fre- quencies. other considerations when designing the input filter include the constraints of the overall system and the actual frequency band of interest. although high-fidelity audio calls for a flat-gain response between 20hz and 20khz, portable voice-reproduction devices such as cel- lular phones and two-way radios need only concentrate on the frequency range of the spoken human voice (typi- cally 300hz to 3.5khz). in addition, speakers used in portable devices typically have a poor response below 300hz. taking these two factors into consideration, the input filter may not need to be designed for a 20hz to 20khz response, saving both board space and cost due to the use of smaller capacitors. bias capacitor bias is the output of the internally generated dc bias voltage. the bias bypass capacitor, c bias , improves psrr and thd+n by reducing power supply and other noise sources at the common-mode bias node. bypass bias with a 2.2? capacitor to gnd. supply bypassing, layout, and grounding proper layout and grounding are essential for optimum performance. use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. large traces also aid in mov- ing heat away from the package. proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. connect pgnd and gnd together at a single point on the pcb. route all traces that carry switching transients away from gnd and the traces/components in the audio signal path. bypass v dd and pv dd with a 1? capacitor to pgnd. place the bypass capacitors as close to the MAX9768 as possible. place a bulk capacitor between pv dd and pgnd, if needed. use large, low-resistance output traces. current drawn from the outputs increase as load impedance decreas- es. high output trace resistance decreases the power delivered to the load. large output, supply, and gnd traces allow more heat to move from the MAX9768 to the air, decreasing the thermal impedance of the circuit if possible. f db in in rc ? = 3 1 2 gnd gnd MAX9768 shdn out 3.3v v dd pv dd in 1 f max1726 12v 1 f figure 10. using a linear regulator to produce 3.3v from a 12v power supply boot+ out+ audio input MAX9768 c in boot- out- in fb r in r f figure 9. setting gain
MAX9768 10w mono class d speaker amplifier with volume control ______________________________________________________________________________________ 23 chip information process: bicmos 23 + 24 22 21 8 7 9 out+ boot+ sclk sda/vol 10 out+ out- boot- v dd out- syncout 12 pgnd 456 17 18 16 14 13 addr2 addr1 bias gnd in fb MAX9768 pv dd pv dd 3 15 pgnd 20 11 gnd mute 19 12 sync shdn tqfn (4mm 4mm) top view pin configuration
MAX9768 10w mono class d speaker amplifier with volume control 24 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 f 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
MAX9768 10w mono class d speaker amplifier with volume control maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. heaney package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 f 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

▲Up To Search▲

Price & Availability of MAX9768

	To Download MAX9768 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .